A static random access memory (SRAM) bitcell includes a pair of cross-coupled inverters. Depending upon the binary state of a stored data bit, a p-type metal oxide semiconductor (PMOS) transistor in one of the inverters may charge a true (Q) data node. Similarly, a PMOS transistor in a remaining one of the cross-coupled inverters may charge a complement (QB) data node depending the binary state of the stored data bit. The Q data node couples through a first n-type metal oxide semiconductor (NMOS) access transistor to a bit line whereas the QB data node couples through a second NMOS access transistor to a complement bit line. During a write operation in which the binary content of the bitcell is changed, one of the PMOS transistors will initially be on and charging its data node while the corresponding access transistor is attempting to discharge the same data node through the corresponding grounded bit or complement bit line. The NMOS access transistor must thus be relatively strong with regard to the PMOS transistor so that the data node can be discharged relatively quickly. To provide this strength, the NMOS access transistors may be relatively large as compared to the inverter PMOS transistors. But increasing the size of the NMOS access transistors reduces density for the resulting SRAM.
To strengthen the NMOS access transistor without such a loss in density, it is thus conventional to provide a negative boost voltage on the otherwise-grounded bit line during the write operation. This negative boost voltage applied during a write assist period increases the strength of the NMOS access transistor in comparison to the inverter PMOS transistor so that the NMOS access transistor can quickly discharge the corresponding data node yet each NMOS access transistor may remain relatively small to enhance density. The negative boost voltage is applied during the write assist period by coupling the appropriate bit line to a charged boost capacitor. But the charge on the boost capacitor is partially discharged to ground at the termination of the write assist period.
This discharge of the boost capacitor charge may be better appreciated with regard to a conventional memory 100 shown in FIG. 1. For illustration clarity, only a single bit line 105 and a memory cell (bit cell) 110 are illustrated in memory 100. Memory cell 110 includes a pair of cross-coupled inverters 115 each having a PMOS transistor (not illustrated) as discussed previously. When a voltage for a word line 120 is asserted high, a Q data node for memory cell 110 couples to bit line 105 through an NMOS access transistor M1. The binary state of bit line 105 depends upon a data signal (DATA) from a write driver (not illustrated) that drive a gate of an NMOS data transistor M5. The drain of data transistor M5 couples to the bit line through a bit line multiplexer 125. Using bit line multiplexer 125, the write driver may write to a plurality of other bit lines (not illustrated) in addition to bit line 105 depending upon the binary state of a write multiplexer control signal that drives a gate of a plurality of NMOS write multiplexer transistors within write multiplexer 125. For example, a write multiplexer transistor M2 couples between the drain of data transistor M5 and bit line 105. Similarly, a write multiplexer transistor M3, a write multiplexer transistor M4, and a write multiplexer transistor M7 all couple between the drain of data transistor M5 and their respective bit lines (not illustrated).
The source of data transistor M5 couples to ground through an NMOS write assist transistor M6. A write assist (negative bit line boost) signal that drives the gate of write assist transistor M6 has a default high state that is pulsed low during the write assist period. Prior to the write assist period, write assist transistor M6 will thus be on such that if the data signal is high, bit line 105 is discharged to ground. The default high state of the write assist signal also passes through a buffer 130 to charge a boost capacitor 135 formed by the gate capacitance of a PMOS transistor P1. The gate of transistor P1 couples to the source of data transistor M5 whereas its drain and source are both coupled to the output of buffer 130. The drain and source of transistor P1 (the anode of boost capacitor 135) will thus be charged high by the buffer output signal as the gate for PMOS transistor P1 is discharged to ground. This discharge of the gate for PMOS transistor P1 occurs through the drain of write assist transistor M6 prior to the write assist period during a write operation in which the data signal is in a binary one state. When the write assist signal goes low, the cathode of boost capacitor 135 (the gate of transistor P1) will thus be pulled below ground due to the gate capacitance for transistor P1. This negative boost for bit line 105 strengthens access transistor M1 compared to the PMOS transistor charging data node Q so that the write operation speed is increased.
The falling edge of the write assist signal is delayed by buffer 130 so that write assist transistor M6 may first be turned off to cause bit line 105 to float so that it may be subsequently pulled to a negative voltage by boost capacitor 135 during the write assist period. Prior to the end of the write assist period, write multiplexer transistor M2 is switched off to isolate bit line 105. Following the rising edge of the write assist signal (i.e., the termination of the write assist period), some of the charge for boost capacitor 135 is then discharged to ground through the switching on of write assist transistor M6. During each write operation, boost capacitor 135 thus discharges an appreciable amount of charge to ground.
Accordingly, there is a need in the art for memories having a negative bit line boost with reduced power consumption.